module mips_datapath(clk,rst,RegDst,RegWr,ExtOp,nPC_sel,ALUctr,MemtoReg,MemWr,ALUSrc,j_sel,Instruction);
  	//module ctrl(instruction,RegDst,RegWr,ExtOp,nPC_sel,ALUctr,MemtoReg,MemWr,ALUSrc,j_sel,rst);
	input clk,rst;
  	input [1:0]ExtOp,ALUctr,nPC_sel;
  	input ALUSrc,MemWr,MemtoReg,RegDst,RegWr,j_sel;
	output [31:0]Instruction;

  	wire [31:0]instruction;
  	wire [31:0]busA,busB,busW,Mux_ALUSrc_out,imm32,Alu_out,Addr,Data_in,Data_out,jValue;
  	wire [31:0]zero;
  	wire [4:0]rw;

  	assign Instruction[31:0]=instruction[31:0];
  
  	//connect all component
	//module ifu(nPC_sel,zero,clk,rst,instruction,j_sel,jValue);
  	ifu IFU(.nPC_sel(nPC_sel),
		.zero(zero),
		.clk(clk),
		.rst(rst),
		.instruction(instruction),
		.j_sel(j_sel),
		.jValue(jValue)
		);

	//module ext(imm16,imm32,ExtOp); 
  	ext EXT(.imm16(instruction[15:0]), //address
		.imm32(imm32),
		.ExtOp(ExtOp)
		); 

	//module alu(busA,busB,ALUctr,zero,Alu_out,Addr);
  	alu ALU(.busA(busA),
		.busB(Mux_ALUSrc_out), //B from ALUSrc
		.ALUctr(ALUctr),
		.zero(zero),
		.Alu_out(Alu_out),
		.Addr(Addr)
		);

	//module mux_RegDst(a1,a0,rw,RegDst);
  	mux_RegDst MUX_RegDst(.a0(instruction[20:16]), //rt
			      .a1(instruction[15:11]), //rd
		  	      .rw(rw),
			      .RegDst(RegDst)
			      );

	//module mux(a0,a1,op,out);
  	mux MUX_ALUSrc(.a0(busB),
		       .a1(imm32),
		       .op(ALUSrc),
		       .out(Mux_ALUSrc_out)
		       );

	//module mux(a0,a1,op,out);
  	mux MUX_MemtoReg(.a0(Alu_out),
			 .a1(Data_out),
			 .op(MemtoReg),
			 .out(busW)
			 );

	//module gpr(RegWr,ra,rb,rw,busW,clk,rst,busA,busB,Data_in); 
	//RegFile
  	gpr GPR(.RegWr(RegWr),
		.ra(instruction[25:21]), //rs
		.rb(instruction[20:16]), //rt
		.rw(rw),
		.busW(busW),
		.clk(clk),
		.rst(rst),
		.busA(busA),
		.busB(busB),
		.Data_in(Data_in)
		);

	//module dm(Data_in,MemWr,Addr,clk,rst,Data_out);
  	dm DM(.Data_in(Data_in),
	      .MemWr(MemWr),
	      .Addr(Addr),
	      .clk(clk),
	      .rst(rst),
	      .Data_out(Data_out)
	      );
  
endmodule

